1. Field
The present embodiments of the invention relate to semiconductor memories, such as NAND flash memories, in which cells are serially connected to form a string. More particularly, the present embodiments of the invention relate to an erase-verify method for semiconductor memories.
2. The Prior Art
Flash memories are electrical programmable and erasable nonvolatile memories commonly used in modern electronic applications. In particular, NAND-type flash memories are becoming ubiquitous in portable data storage applications such as mobile phones, digital still cameras, mp3 players, etc. because of their characteristics of high-density and fast operations.
In NAND flash devices, the floating-gate memory cells are arranged in strings. A string consists of a series of flash cells that are connected to a bit line by means of a bit-line select transistor and to a common source line by means of a ground-select transistor. Such an arrangement is shown in FIG. 1, in which flash memory cells 12, 14, 16, and 18 are shown connected to bit line 20 through bitline select transistor 22 and to common source line 24 through ground-select transistor 26 to form a first string.
NAND strings are arranged to form a memory matrix as also shown in FIG. 1 in which, as an example, four strings of cells are shown. A second string includes flash memory cells 28, 30, 32, and 34 are shown also connected to bit line 20 through a bit-line select transistor 36 and to the common source line 24 through ground-select transistor 38. A third string includes flash memory cells 40, 42, 44, and 46 are shown connected to second bit line 48 through a bit-line select transistor 50 and to the common source line 24 through ground-select transistor 52. A fourth string includes flash memory cells 54, 56, 58, and 60 are shown also connected to the second bit line 48 through a bit-line select transistor 62 and to the common source line 24 through ground-select transistor 64. Persons of ordinary skill in the art may assume that, although each string is shown including four memory cells, the following discussion is based on each string containing sixteen cells.
In such a matrix organization, a portion of which is shown in FIG. 1, strings that share the same set of bit lines are connected to different word lines and strings connected to the same word line are controlled by different bit lines. Thus, bit word line 66 is coupled to the gates of bit-line select transistors 22 and 50. Similarly, the word line 68 for the first bits in the two strings in the top row of the portion of the matrix shown is coupled to the gates of flash transistors 12 and 40. The word line 70 for the second bits in the two strings in the top row of the portion of the matrix shown is coupled to the gates of flash transistors 14 and 42; the word line 72 for the fifteenth bits in the two strings in the top row of the portion of the matrix shown is coupled to the gates of flash transistors 16 and 44; the word line 74 for the sixteenth bits in the two strings in the top row of the portion of the matrix shown is coupled to the gates of flash transistors 18 and 46. The word line 76 for the ground-select in the two strings in the top row of the portion of the matrix shown is coupled to the gates of flash transistors 26 and 52.
In the two strings in the bottom row of the portion of the matrix shown, bits seventeen through thirty-two are shown. Bit word line 78 is coupled to the gates of bit-line select transistors 36 and 62. The word line 80 for the seventeenth bits in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 28 and 54. The word line 82 for the eighteenth bits in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 30 and 56; the word line 84 for the thirty-first bits in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 32 and 58; the word line 86 for the thirty-second bits in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 34 and 60. The word line 88 for the ground-select in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 38 and 64. The word line 88 for the ground-select in the two strings in the bottom row of the portion of the matrix shown is coupled to the gates of flash transistors 38 and 64.
As is shown in FIG. 2, the source line 24 is usually common to a sector or a bank of the matrix, shown within dashed lines 100 in FIG. 2. The illustrative sector 100 in FIG. 2 shows a plurality of strings 102, 104, 106, 108, 110, 112, 114, and 116 connected to different word lines and to different bit lines but sharing the same source line 24. All the cells in the same memory sector or bank are fabricated within the same p-well substrate.
To illustrate read, program and erase operations of NAND flash memory, a particular case of one bit per cell memory is considered. However, persons of ordinary skill in the art will appreciate that the principles disclosed herein apply both to single level flash memories (one bit per cell) and to multilevel flash memories (many bits per cell). For purposes of his disclosure, programmed cells have positive thresholds while erased cells have negative thresholds.
When a cell in the matrix is read, a determination is made whether the given cell has a positive threshold or a negative threshold. This determination is made by applying a zero-bias voltage (Vread=0) to the word line of the selected cell and by applying a positive read-pass voltage (Vread-pass>0) to the word lines of the other cells and to select transistors of the same string. The read-pass voltage must be high enough to turn on the unselected cells in the string, i.e., it must be higher than the maximum threshold of programmed cells in order to assure that the unselected cells are all turned on. A typical value for Vread-pass is 4.5V.
Depending on sensing technique employed, the bit line of the selected string is biased (current sensing) or pre-charged (voltage sensing) to a positive voltage (e.g. VBLread=1V) while other bit lines are kept grounded or floating. If the selected string sinks current through the bit line then the selected cell is erased otherwise it is programmed. The bias voltages for read operation are shown in Table I, assuming that it is desired to read the contents of memory cell 42 of FIG. 1.
Signal NameBiasWL-BSL1Vread-passWL1Vread-passWL2VreadWL3 through WL16Vread-passWL-SL1Vread-passVBL10 VVBL2VBLreadWL-BSL20 VWL17 through WL320 VWL-SL20 V
Programming of a cell consists of moving a cell threshold value from its initial negative-value state (erased state or native state) to a positive value. This is performed exploiting Fowler-Nordheim (FN) tunneling in floating-gate transistors by applying a high program voltage (for example Vpgm=18V) to the word line of the cell to be programmed, and by applying an intermediate pass voltage (for example Vpass-pgm=9V) to the cells in the same string in which programming is to be inhibited. This will cause tunneling of electrons onto the floating gate to give it a net negative charge.
An erase operation shifts the threshold distribution of the cells to be erased from a positive value (programmed state) back to a negative value (erased state or native state). Erase is a parallel operation, i.e. many cells are erased at a time and the erase of a single cell is not permitted. Usually, in NAND flash devices, the minimum erasable unit consists of all the cells in strings that share the same set of word lines. More than one minimum erasable unit can be erased at the same time. Erasing is performed by applying a positive high voltage (for example Verase=18V) to the p-well bulk area of the selected bank and by biasing to ground all the word lines of the units to be erased. This will cause tunneling of electrons off of the floating-gates of the cells biased at ground to give them a net positive charge and thus shift their thresholds back to their native negative value.
After every erase attempt, an erase verify operation is needed to determine whether all the cells have been successfully erased. If erase verify fails, another erase pulse is needed.
As will be appreciated by persons of ordinary skill in the art, an erase-verify operation can be performed either serially or simultaneously, the serial verify operation consists of individually verifying every single cell to be erased one at a time. This involves applying the read bias voltage (Vread=0) to the selected word line, applying a pass voltage (Vpass-read) to the unselected word line of the same unit and performing a read operation. The sequence needs to be repeated for all the word lines of the unit to be verified. Serial verify is very slow especially when long strings are used.
Simultaneous erase verify is faster than serial erase verify, and it consists of simultaneously biasing at ground (Vread) the word lines of the unit to be verified and performing a single read operation. If all the cells have been successfully erased, all strings biased at ground sink current from their respective bit lines and verify is passed. On the other hand, if just a single cell in the unit has a voltage threshold that remains higher than ground, it will not conduct and its string does not sink current. In this case, the verify fails and another erase pulse is attempted on that unit.
If more than one unit is erased in parallel, either serial or simultaneous verify need to be serially applied to all units. A new erase pulse is given only to those units that fail to pass erase verify.
Simultaneous erase verify is the most commonly used in NAND flash memories. However, this method has two drawbacks.
The first problem arises from the fact that, during erase verify, all the cells are simultaneously grounded. Due to this bias condition, the overdrive voltage of each cell is relatively low, even for correctly erased cells (i.e., for cells with negative thresholds). Because cells in a string are serially connected, the overall equivalent series resistance of the string is higher than it would be during a read operation (i.e., when only one cell is grounded and other cells are biased at Vpass-read). This implies a low verify current that is critical for both current sensing and voltage sensing methods.
If a current sensing technique is used, the read circuit compares the string current with a reference current. Low-current operations impact sense circuit precision and speed. Moreover noise and disturbs might negatively affect circuit operation. Under these conditions, the design of the sense circuit becomes more critical.
If a voltage sensing technique is used, the bit line is pre-charged to a given value. If the erase operation is successful, the bit line will be discharged by the string current. In this case, operating with a low current means that a long time is required to discharge the bit line.
If not enough time is allowed for bit-line discharge, there is the risk of ending up with over-erased cells. If enough time has not elapsed to fully discharge the bit line, correctly-erased cells might be misinterpreted by the read buffer due to insufficient bit-line discharge, and sensed as still programmed. In this case another erase pulse would be applied and would likely over-erase the cells. It is worth noting that over-erase is not recommended in NAND flash memories because it slows erase operation (unnecessary erase pulses are applied) and unnecessarily over stresses cells, a process that can negatively impact on device cycling performances.
The second problem inherent in simultaneous-erase verify is caused by control-gate-to-floating-gate and floating-gate-to floating-gate interference effects of adjacent cells. As NAND flash memory design rules are scaled down, the cell pitch in the string decreases and parasitic coupling capacitances between adjacent cells play an increasingly important role.
Consider any cell to be read in a particular string in FIG. 1, and assume the cells in the string are all erased. In read operations, adjacent cells are biased to 4.5V, while in simultaneous-erase verify adjacent cells are grounded. Therefore, during read operations, adjacent cell bias tends to facilitate selected cell turn-on because of parasitic coupling, resulting in a lower apparent threshold voltage for the selected cell with respect the case of erase-verify operation. In fact, in the latter case, when adjacent cells are grounded, parasitic coupling does not influence selected cell turn-on, and the voltage threshold appears to be higher than in the read case. Therefore, the simultaneous-erase verify method may lead to cell over-erase caused by unnecessary additional erase pulses.